Stability Analysis of 6T SRAM at 32 Nm Technology
نویسندگان
چکیده
ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the stability of SRAM. This paper investigates Static random access memory (SRAM) stability in hold/standby, read and write mode. In this paper different techniques to find Static Noise Margin (SNM), Read margin and write margin are discussed. The effect of supply voltage, transistor scaling, word line voltage, threshold voltage, and temperature on SRAM stability is analysis in Standby and Read Mode. From 0.7V to 1.2V the read stability increase 231% and Standby stability increase 135%. When the cell ratio changes from 1 to 3 the stability of SRAM during read mode gets doubled. This paper also investigate the Data Retention Voltage(DRV) during standby and read mode which is the minimum voltage required to hold or read data, any voltage below DRV can flip the state of SRAM. The DRV 6T SRAM in Standby mode is 0.14V and that in read mode is 0.29V.
منابع مشابه
12th Int'l Symposium on Quality Electronic Design
Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Te...
متن کاملArea Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme
This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the are...
متن کاملA new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology
A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to...
متن کاملComparative Parametric Analysis for Stability of 6t and 8t Sram Cell
As the technology is improving , channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. Static noise margin (SNM)[1] plays a vital role in stability of SRAM[2]. This paper gives an introduction to the “8T SRAM cell”[3]. It includes the Implementation, characterization and analysis of 8T SRAM cell and its comparison with t...
متن کاملStability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications
Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its...
متن کامل